A 2-pixel 1-cell type structure is well known as a cell structure of a conventional CMOS sensor-type solid-state imaging device. The 2-pixel 1-cell structure is a so-called shared pixel-type in which two photodiodes (hereinafter referred to as PDs) are provided to accumulate charges generated by photoelectric conversion and an output circuit to convert signal charges read from the PDs into a voltage is shared by the two PDs. Typical examples of the shared-pixel-type structure are described in U.S. Pat. No. 6,091,449 or Japan Patent Publication 2006-302970 filed by the present applicant.
A solid-state imaging device of the 2-pixel 1-cell type include PDs, a floating junction (hereinafter referred to as an FJ) configured to transfer charges from the PDs, transfer gate transistors (hereinafter referred to as TGs) configured to control the transfer the charge of the floating junction, an output amplifier transistor (hereinafter referred to as an Amp) configured to detect a variation in potential of the FJ, a gate electrode of a reset transistor (hereinafter referred to as an RS) configured to reset the potential of the FJ to a constant potential before the charges from the PDs are transferred to the FJ, and a reset drain electrode (hereinafter referred to as an RD) serving as a reset potential of the RS and a power source of the Amp. An output source electrode (hereinafter referred to as an OS), which is configured to externally output a variation in potential of the gate electrode connected to the FJ, is provided at a side of a source electrode of the Amp.
Thus, each PD includes a TG configured to transfer charges, and two PDs share the FJ, the RS, the Amp, and the RD may be shared by the two PDs. Thus, element isolation regions increase since the above-described components are provided around each PD. Typically, the number of transistors of the 2-pixel 1-cell type structure includes two TGs, one RS, and one Amp, and thus two transistors are required for each PD. Further, with respect to the number of wirings, there are two TG wirings, one RS wiring, one RD wiring, and one output wiring (connected to an OSL) for two PDs, in a 2-pixel 1-cell type structure in which 2 PDs are arranged in a vertical direction. Thus, one TG wiring (horizontal direction), 0.5 RS wiring (horizontal direction) and RD wiring (horizontal direction), and one output wiring (vertical direction) are required for each PD.
Regarding the element isolation region, since element isolation is necessary between a PD and a transistor in typical fine cells, the isolation is made in a structure which is referred to as shallow trench isolation (hereinafter referred to as STI). This is a method of forming a shallow groove (trench) in a semiconductor substrate to form an isolated structure by burying an oxide layer in the shallow trench. To prevent image deterioration (white scratches) caused by damage applied when forming the trench in the semiconductor substrate, designs in which an impurity region is prepared around the trench such that a depletion layer from the PDs does not reach a damaged region are being proposed. While the providing of the impurity region contributes to image quality improvement, an effective area of the PD is reduced. In addition, charges that may be accumulated in the PDs (hereinafter referred to as saturation charges) may be reduced when the fine patterning of pixels is performed.
Meanwhile, an increase in the number of wirings has led to a lowering of effective collection of light incident to the PDs, thus causing shading deterioration even in a screen peripheral portion. Similarly, these problems have resulted in image deterioration along with the finer patterning of the cells.